Resilient Endurance-Aware NVM-based PUF against Learning-based Attacks

Hassan Nassar, Ming-Liang Wei, Chia-Lin Yang, Jörg Henkel, Kuan-Hsun ChenarXiv 2025 · DOI

Introduction

Physical Unclonable Functions (PUFs) serve as the "digital fingerprints" of hardware, leveraging inherent manufacturing variations to generate unique cryptographic keys. While traditional PUFs are vulnerable to Machine Learning (ML) modeling attacks, the integration of Non-Volatile Memory (NVM) has emerged as a promising countermeasure. NVMs introduce complex, non-linear behaviors that are difficult for ML models to replicate. However, NVM-based designs face a significant hurdle: limited endurance. Frequent write operations during authentication cycles lead to rapid "wear-out," rendering the security hardware unusable over time.

The Challenge: Security vs. Longevity

The primary conflict in NVM-based PUF design is between high security (which often requires frequent state changes to thwart modeling) and device lifespan. Traditional NVM cells have a finite number of write cycles. In a security context where every challenge might trigger a write, these devices often fail prematurely. Researchers have sought a solution that maintains the non-linear complexity needed to defeat ML attacks without sacrificing the physical integrity of the memory cells.

Proposed REAP-NVM Architecture

To address these issues, researchers developed REAP-NVM, a resilient and endurance-aware PUF architecture. The design builds upon the classic Arbiter PUF structure but integrates multi-level NVM cells into the signal paths.

Extracted figure from page 4 of Resilient Endurance-Aware NVM-based PUF against Learning-based Attacks

The architecture employs several key innovations:

  • Selective Writing Strategy: Instead of updating every cell for every challenge, REAP-NVM only writes to a single pair of cells per challenge. This drastically reduces the average wear per cell.
  • Multi-Level Complexity: By utilizing eight different resistance levels per NVM cell, the design creates highly non-linear signal delays. This complexity makes it nearly impossible for an attacker to build an accurate digital twin of the hardware.
  • Endurance Modeling: The team utilized Markov Chain frameworks to predict cell transitions and deduce the overall lifetime of the PUF, ensuring it meets practical operational requirements.

Evaluation and Results

The performance of REAP-NVM was evaluated using high-fidelity SPICE and Matlab simulations, with parameters derived from real-world Phase Change Memory (PCM) data. The study compared REAP-NVM against standard Arbiter PUFs and other state-of-the-art NVM designs.

Security and Reliability

In ML modeling attacks using 90,000 training samples, attackers achieved only ~55% accuracy against REAP-NVM—barely better than a random guess. In contrast, a standard Arbiter PUF was cracked with 95% accuracy. Furthermore, the design demonstrated excellent statistical properties.

Extracted figure from page 5 of Resilient Endurance-Aware NVM-based PUF against Learning-based Attacks

As shown in the figure above, the design achieves near-ideal scores for Uniqueness and Uniformity (centered at 50%), ensuring that the generated responses are both distinct across devices and balanced in their bit distribution.

Endurance and Efficiency

The "Selective Write" approach yielded a 62x increase in endurance compared to the best existing NVM-PUF designs. REAP-NVM can withstand significantly more authentication cycles before reaching the 15% cell-death failure threshold. Additionally, the design is energy-efficient, consuming only 752 nJ per operation.

Conclusion

REAP-NVM represents a significant leap forward in hardware security. By combining the non-linear advantages of multi-level NVM with a clever selective writing strategy, it successfully thwarts advanced machine learning attacks while solving the critical wear-out problem. While the design requires a larger physical footprint (256 cells per response bit), its superior durability and security make it a robust candidate for long-term deployment in secure hardware environments.