Introduction
In the field of Electronic Design Automation (EDA), the ability to identify specific sub-circuits within a larger netlist is fundamental to optimization, hardware security, and design verification. Traditionally, this task has been framed as a subgraph isomorphism problem—a search for an exact structural replica of a query graph within a target design. However, modern logic synthesis tools are designed to aggressively transform circuit topology to optimize for power, performance, and area (PPA). These transformations create a "structural gap" where two circuits may be functionally identical but structurally unrecognizable to traditional algorithms.
This paper introduces a novel deep-learning framework for functional subgraph matching. By shifting the focus from how a circuit is wired to what it actually does, the authors provide a robust method for identifying logic components even after they have been obfuscated or restructured by synthesis tools.
The Challenge: The Structural Gap in EDA
Logic synthesis and technology mapping are the primary hurdles for structural matching. For example, the Boolean expression $a \times b + a \times c$ can be structurally represented as two multipliers and an adder. A synthesis tool might optimize this to $a \times (b + c)$, which uses only one multiplier and one adder. While the logic remains the same, the graph structure changes entirely.
Existing structural matching algorithms, such as the VF2 algorithm, fail the moment these optimizations occur. To address this, the authors propose a method that identifies functional containment—the presence of a specific Boolean function within a larger netlist—regardless of the physical implementation.
Proposed Methodology: A Two-Stage Framework
The authors approach functional matching through a two-stage multi-modal framework designed to align abstract logic with physical netlists.
1. Functional Subgraph Detection
The first stage determines whether a query's logic exists anywhere within the target graph. This is achieved using a multi-modal embedding approach that leverages specialized backbones:
- DeepGate2: Used for processing abstract And-Inverter Graphs (AIGs).
- DeepCell: Used for processing post-mapping gate-level netlists.
To bridge these modalities, the framework employs InfoNCE loss for both intra-modal and inter-modal alignment. This contrastive learning strategy ensures that different structural implementations of the same Boolean function are mapped to nearby points in a latent embedding space. The result is a "function-invariant" representation that allows the model to "see through" synthesis transformations.
2. Fuzzy Boundary Identification
Once a match is detected, the second stage locates the specific gates comprising that logic. The authors define a "Fuzzy Boundary" as the minimal region in the target graph that encapsulates the query's logic.
Unlike previous attempts that treated this as a node-by-node classification problem, this paper formulates boundary identification as a graph segmentation task. By training the model to recognize the continuous flow of information from inputs to outputs, the framework ensures that the identified subgraphs are cohesive and logically complete, rather than a collection of disconnected nodes.
Experimental Results
The framework was evaluated using several standard EDA benchmarks, including ITC99, OpenABCD, and ForgeEDA. To test scalability, the researchers also utilized a custom subset of ForgeEDA containing circuits ranging from 100 to 10,000 nodes.
Key performance metrics include:
- Detection Accuracy: The model achieved an average accuracy of 93.8% across benchmarks, significantly outperforming structural methods which often fell to near-random performance (approx. 50%) on synthesized designs.
- Localization Precision: The boundary identification stage achieved a 91.3% Dice score, demonstrating high precision in isolating functional logic from the surrounding circuit noise.
- Robustness: The model maintained high performance even when synthesis was specifically configured to maximize structural divergence from the original query.
Discussion and Future Work
While the proposed framework represents a significant leap forward, several challenges remain. The current model's performance begins to decline on very large netlists exceeding 10,000 nodes, suggesting a need for hierarchical processing or incremental segmentation. Additionally, the current implementation assumes single-output logic blocks. Real-world designs often feature shared internal logic across multiple outputs, a complexity that future iterations of the framework will need to address.
By moving beyond structural isomorphism to functional alignment, this research provides a more resilient foundation for automated circuit analysis in the age of aggressive logic optimization.